The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with vertical gates and a method for fabricating the semiconductor device.
Decreasing design rules of Dynamic Random Access Memory (DRAM) has brought about much difficulty in the fabrication of DRAM of under 40 nm-class. To overcome the difficulty, researchers have sought to form vertical gates instead of planar gates.
In a semiconductor device with vertical gates, a vertical gate is fabricated by processing a substrate to have an active pillar including a neck pillar and a top pillar and by growing a gate insulation layer. As the vertical gate has a structure of surrounding the external walls of the neck pillar of the active pillar, a channel stretched in a vertical direction is formed between the upper part and the lower part of the active pillar.
Dividing an active pillar into a neck pillar and a top pillar works as an obstacle to high integration because it makes a space between top pillars. Specifically, the active pillar may collapse due to weak supporting force of the neck pillar, which is problematic.
To solve this problem, a neck-free vertical gate capable of securing space between active pillars and preventing pattern collapse was suggested. The neck-free vertical gate refers to a vertical gate structure surrounding a straight line-type active pillar without a neck pillar.
FIG. 1A is a plan view illustrating a conventional semiconductor device having a neck-free vertical gate, and FIG. 1B is a cross-sectional view showing the conventional semiconductor device of FIG. 1A taken along a line A-A′.
Referring to FIGS. 1A and 1B, active pillars 12 are formed over a substrate 11, and a hard mask layer 13 is formed over the active pillars 12. The external walls of each active pillar 12 are surrounded by the gate insulation layer 14 and a vertical gate 15. Inside the substrate 11, buried bit lines 16 are formed through impurity ion implantation. Adjacent buried bit lines 16 are separated from each other by trenches 17.
The above-described prior art describes a structure to be applied to a DRAM having a design rule of 4F2, where F denotes minimum feature. Since the structure does not have a neck pillar, it can stably form the active pillar.
However, the above method can hardly secure dimensions for a process of forming buried bit lines through impurity ion implantation if the DRAM has a high integration design rule of under 3F2, whose integration degree is higher than that of the 4F2.